1. Field of the Invention
The present invention relates to a matrix type multiple numeration system ferroelectric random access memory using leakage current, which is non-volatile and with which it is possible to realize a multiple numeration system using the leakage current of a dielectric or a ferroelectric, and a method for manufacturing the same.
2. Description of Related Art
In general, a random access memory cell includes a field effect transistor and a linear capacitor. Because a linear capacitor has two electrodes and a dielectric interposed between them, it is possible to store data using a charging phenomenon caused by the polarization of the dielectric. However, the charge stored in the dielectric of a linear capacitor cannot function as a memory unless cells are periodically recharged or refreshed since the capacitor naturally discharges. Therefore, a function of periodically refreshing the cells must be added. Also, once power is turned off, the capacitors are all discharged and the information is deleted, since the function of refreshing the cells stops. Namely, the memory is volatile.
A memory using a ferroelectric capacitor, in which a ferroelectric material is used as a dielectric material, was provided in order to achieve a non-volatile memory. In general, information is easily stored in the ferroelectric capacitor without refreshing the cells, since charge stored by the polarization is not discharged due to the physical characteristic of the ferroelectric material. Read methods include a destructive read out (DRO) method, for reading a memory state by sensing the signal generated by applying a uniform signal to the ferroelectric capacitor, which switches the polarization state, and a non-destructive read out (NDRO) method, in which polarization switching occurs only when writing is performed and does not occur when reading is performed. Fatigue due to the switching of the polarization state is cumulative, thus the polarization state of the ferroelectric gradually weakens as the ferroelectric capacitor is repeatedly switched in order to read/write information therein. Therefore, the NDRO method is advantageous to the prolongation of memory life. The 1T-1C FRAM of Ramtron is representative of the DRO method. The SFRAM of Radiant Technologies and the metal-ferroelectric-metal-insulator-Si (MFMIS) of Rohm are representative of the NDRO method. However, it is not possible to completely solve the fatigue problem of the ferroelectric by the above-mentioned methods, since write switching must be performed when writing information to the memory element.
Multiple numeration system memories can store information of multiple states. Examples of such memories are the 4 terminal transistor and neuron MOSFET of Shibata and the partial switching MFS FET of Ishiwara. Hereinafter, the operation principle of the 4 terminal transistor and neuron OSFET of Shibata will be described with reference to FIGS. 1 through 5.
As examples of devices having different numbers of terminals, a diode (not shown) is a two terminal element, the FET shown in FIG. 1 is a three terminal element, and the FET having two gates shown in FIG. 2 is a four terminal element. Here, the three terminal element and the four terminal element each have a source (S) and a drain (D), the three terminal element has a gate (G), and the four terminal element has two gates (G.sub.1 and G.sub.2). The operation characteristics of the three and four terminal FETs are as follows.
In the case that the drain voltage V.sub.DS (the voltage between the source and drain) is uniform, the characteristic curve of the drain current (from the source to the drain) which flows through each of the three and four terminal elements according to a gate voltage (V.sub.G or a combination of V.sub.G1 and V.sub.G2) is shown in FIGS. 1 and 2, respectively. In the case of the three terminal element, the drain current I.sub.D is a single curve, but in the case of the four terminal element the I.sub.D curve is multiple, according to the increase of V.sub.G2 voltage.
The characteristics of the drain current I.sub.D will be described in more detail with reference to FIGS. 3 and 4.
In the three terminal element, as shown in FIG. 3, the drain current increases according to the increase of the gate voltage V.sub.G, in the saturation area of V.sub.DS. In the four terminal element, as shown in FIG. 4, the characteristic curve of the drain current is three-dimensionally depicted. The drain current increases according to the increase of the first gate voltage V.sub.G1 in the saturation area (marked with the dotted line) of V.sub.DS. The rate of increase is enlarged according to the increase of the second gate voltage V.sub.G2.
The neuron MOSFET shown in FIG. 5 was developed as a multiple terminal element utilizing the drain current characteristics of the four terminal element. The neuron MOSFET forms a floating gate, thus forming n multiple gates. When a signal voltage is applied to each of the n multiple gates, the neuron MOSFET having a threshold voltage of V.sub.th is turned on in the following condition. EQU .PHI.F=(C1V.sub.1 +C2V.sub.2 + . . . +CnV.sub.n)/C.sub.tot &gt;V.sub.th
It is possible to record multiple state information utilizing the above characteristics of the four terminal transistor or the neuron MOSFET transistor of Shibata, although the latter has a problem of being volatile. The MFS FET of Isawara is non-volatile since the ferroelectric is used, however, the fatigue rate of the ferroelectric is severe. Also, materials for forming the ferroelectric used in a memory are restricted to those which can be directed deposited on Si.